Model Based FPGA Design of Histogram Equalization

F. MEMON, F. JAMEEL, M. ARIF, F. A. MEMON

Abstract


Histogram equalization is a preliminary process for image processing and enhancement, with a key focus on hardware implementations, real-time applications and fast performance. In this paper, a novel approach using Model Based Design for hardware implementation of histogram equalization algorithm into Field Programmable Gate Array (FPGA) is presented. The proposed methodology assists to develop and prototype the design in a comparatively short time by removing time consuming and tedious work due to manual coding. With the Model Based Design, MATLAB model of histogram equalization is translated into FPGA hardware implementation via HDL Coder. The design is implemented on Xilinx Virtex5 FPGA device and can work with an estimated frequency of 183.733MHz by occupying less than 5% of available hardware with total power consumption of 0.367W. Experimental results suggest that the proposed design methodology provides an equalized image comparable in accuracy to the full precision MATLAB’s output, and generates output image of size 494 x 335 pixels in 0.9057msec vs 10.845sec in MATLAB, that is much faster than real time video rate.

Full Text:

PDF

Refbacks

  • There are currently no refbacks.


Copyright (c) 2016 Sindh University Research Journal - SURJ (Science Series)

 Copyright © University of Sindh, Jamshoro. 2017 All Rights Reserved.
Printing and Publication by: Sindh University Press.